Author(s)

Can Zhao ¹, Jun Yang ¹

Affiliation(s)

¹ School of Information Science and Engineering, Yunnan university, Kunming, China

Corresponding Author

ABSTRACT

With the increasingly developed processing speed of the processor, the processing speed of the FFT is also higher than that of the past. However, the design of the FFT processor based on FPGA is still dominated by the single core[1]. This design is mainly used for the single nuclear FFT processor where the multi-core era faced the FPGA-based parallelization of the technology. The system uses Verilog HDL language, in the Quartus II 8.0 development platform for layout and routing test, and the final A dual-core FFT processor based on FPGA is implemented.

KEYWORDS

CITE THIS PAPER

Can, Z. , Jun, Y. (2017) Dual-core FFT Processor Based on FPGA. Journal of Electronics and Information Science (2017) 2: 84-87.

REFERENCES

[1] Ferreira M L, Barahimi A, Ferreira J C. Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications[M]// Applied Reconfigurable Computing. Springer International Publishing, 2016.
[2] Jianbiao H E, Communication D O, Polytechnic S. Configurable FFT Processor Based on FPGA[J]. Ship Electronic Engineering, 2016.
[3] Xia K, Wu B, Zhou X, et al. An efficient prime factor memory-based FFT processor for LTE systems[C]// IEEE International Symposium on Circuits and Systems. IEEE, 2016:1546-1549.
[4] Yin X W, Tan H Z. A mixed radix based parallel pipeline FFT processor for MB-OFDM based UWB systems[C]// International Conference on Wireless Communication and Sensor Network. 2016:494-500.
[5] Wang B, Zhang Q, Ao T, et al. Design of Pipelined FFT Processor Based on FPGA[M]. 2010.
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