Author(s)

Yuming Zhang ¹, Huanqing Xu ¹, Jun Yang ¹

Affiliation(s)

¹ School of Information Science and Engineering, Yunnan university, Kunming, China

Corresponding Author

Yuming Zhang

ABSTRACT

This paper not only describes the design of a central overhead ETC lane and the lane controller, canceling the traditional Lane rail to achieve a transparent ETC to the user, but also effectively solves problems of congestion. And by optimizing the internal structure of the ETC baseband circuit, this paper uses the FPGA technology to achieve the international standard of B baseband codec - Manchester codec.

KEYWORDS

Electronic toll collection system, FPGA, lane layout, HDLC.

CITE THIS PAPER

Yuming, Z. , Huanqing, X. , Jun, Y. (2017) Research and Design of ETC System’s Key Technologies Based on FPGA. Journal of Electronics and Information Science (2017) 2: 88-92.

REFERENCES

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[3] Nowacki, Gabriel, Niedzicka, Anna.Polish Research on the Subject of Electronic Toll Collection [C].Warsaw, Poland, Motor Transport Institute, Jagiellonska 80, 03-301, 2011.
[4] Analyzing Performance of ETC Plazas Using New Computer Software.Comp.in Civ.Engrg,2001,15(4): 309-319.
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[9] Wang-Cheng H U. Design and Implementation of Contactless IC Card in the ETC System for National Standard[J]. Microcomputer Information, 2009, 366(1):114–121.

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