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Hardware Implementation of AES Encryption Algorithm Based on FPGA

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DOI: 10.23977/jeis.2017.22007 | Downloads: 52 | Views: 4513


Huanqing Xu 1, Yuming Zhang 1, Jun Yang 1


1 School of Information Science and Engineering, Yunnan university, Kunming, China

Corresponding Author

Huanqing Xu


With the development of society, the information industry has attracted more and more attention by the state. Since the emergence of prism doors, it has made countries pay great attention to the direction of information security. The question about how to protect information security has become an increasingly concerned issue. This paper introduces a widely used algorithm based on FPGA of symmetric encryption algorithm AES, because its key has three kinds of length 128bit, 192bit, 256bit, which can guarantee its difficulty in the crack, so it is relatively safe, this design can include encryption path and decryption path, you can also shield the decryption path and only include the encrypted path to reduce the use of resources in order to apply to resources insufficiently when the data is encrypted. Besides, this article can also be used for the key and data transmission using 32bit bus, multi-clock transmission. Through the Jtag Uart module to achieve the computer and embedded system communication, you can use it in the IDE integrated environment to achieve the program window to debug and monitor.


FPGA, AES encryption, Nios II, asymmetric encryption.


Huanqing, X. , Yuming, Z. , Jun, Y. (2017) Hardware Implementation of AES Encryption Algorithm Based on FPGA. Journal of Electronics and Information Science (2017) 2: 93-97.


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