Author(s)

Liu Fan, Huang Wei, Cui Huarui, Huang Xiaozong, Liu Zhiwei

Corresponding Author

Liu Fan

ABSTRACT

A failure analysis of a Phase lock loop (PLL) due to the ESD structure defects is presented in this paper. ESD is one of the most important reliability issues in the design of integrated circuits. About 40% of the failure of integrated circuits is related to ESD/EOS stress. In order to improve the reliability of ICs, the design of ESD protection is increasingly necessary for the modern semiconductor industry [1, 2]. There are many standards to evaluate the ESD robustness of a circuit, and the HBM and MM model are the most popular criteria. To improve the ESD capability and find out the root of the failure phenomenon, this paper employs some FA tools to deal with the problems, and the optimized solution is given and discussed, which can effectively improve the reliability of the product.

KEYWORDS

ESD Protection, CMOS Process, Layout design, Failure Analysis