Education, Science, Technology, Innovation and Life
Open Access
Sign In

A Simulation-based Fault Injection Mechanism of Digital Circuit

Download as PDF

DOI: 10.23977/acsat.2017.1006


Zhou Quan, Yan Xin, Yang Liang

Corresponding Author

Quan Zhou


Fault injection is a key step in the validation of fault-tolerant design. This paper introduces a novel simulation-based fault injection method. The proposed method is implemented directly in Test Bench (TB) by modifying the signal values in VHDL model, and the fault type and ratio, transient fault duration and fault injection rate etc. can be easily adjusted according to requirements. It also supports the random fault injection by giving a random distribution. Compared with existing approaches, this simple method that can be designed and used immediately has a better extendibility and a better tailing capability due to the fact that it is field programmable in TB. Fault injection experiment shows that this approach is flexible and easy to use.


VHDL, test bench, fault-tolerance, reliability design, reliability validation, fault injection.

All published work is licensed under a Creative Commons Attribution 4.0 International License.

Copyright © 2016 - 2031 Clausius Scientific Press Inc. All Rights Reserved.