Author(s)

Zijian Huang

Corresponding Author

ABSTRACT

As an important part of the design of SRAM-FPGA system, registers are vulnerable to soft errors caused by high-energy particles in the space environment. The three modular redundancy design method can protect the register from fault tolerance, but it brings a lot of resources and power consumption. Aiming at this problem, this paper designs a dual-mode redundancy protection structure based on parity check, which takes flip-flops as units and takes advantage of the structure characteristics of FPGA lookup table. The two flip-flops are designed as a group of fault-tolerant devices. By choosing the correct result output through parity check, the data bits of registers can be misshielded from fine-grained aspects. This method is verified in the history of Xilinx Virtex®-6FPGA. Experimental results show that the design of registers relative to three modular redundancy can reduce 16.7% of trigger resources and 50% of look-up table resources.

KEYWORDS

FPGA; SRAM; Register; Dual Modular Redundancy