VHDL Based Parallel/Serial Conversion
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DOI: 10.23977/CNCI2020015
Author(s)
Qiqi Gong, Yueze Gu and Yuanyuan Zhang
Corresponding Author
Qiqi Gong
ABSTRACT
In this paper, the method of designing a process-observable 8-bit parallel/serial conversion system is introduced. Parallel/Serial conversion is a common concept in data processing and communication area. However, with the upgrading of FPGA, quicker process frequency is required and basic chips used to conduct parallel/serial conversion seem to fall behind due to low frequency and unreliable data transmission. Sometimes, the process frequency should be adjusted while the global clock has been given certain frequency. Also, there is a lack of research into VHDL based conversion system. The parallel/serial conversion system designed in this paper is composed of three parts: a 32-bit counter used to adjust clock frequency, a parallel-to-serial converter based on synchronous D flip-flops with an En pin and a serial-to-parallel converter. Reliable data transmission is realized by a periodic impulse Fn. When the transmission is completed, it sends out a high level signal to indicate compliment. Implementation of the system is conducted in VHDL. Simulations and physical experiments verify the rationality of the system.
KEYWORDS
VHDL; parallel/serial conversion; FPGA