Author(s)

Pei Xiaohe, Shan Tao, Liu Shengheng, Feng Yuan

Corresponding Author

Pei Xiaohe

ABSTRACT

The scale of the sequential data sets to be real-timely processed in most sectors of digital signal processing has substantially increased, making efficient numerical algorithms such as sparse fast Fourier transform (SFFT) more attractive than ever. This paper presents an improved FPGA-based SFFT implementation scheme, where a novel pipeline shift queue structure and a novel pipeline tracking filter structure are designed to significantly reduce the computational complexity. With the proposed scheme, millions of SFFT modules can be integrated on a single Virtex-6 FPGA chip, in addition to which, no assumptions or a priori knowledge on the spectrum distribution of the input signal is required.

KEYWORDS

Digital signal processing, sparse fast Fourier transform (SFFT), hardware implementation architecture, field-programmable gate array (FPGA).