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An Investigation of Race Hazard Elimination in Digital Counter Circuits

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DOI: 10.23977/jeeem.2025.080117 | Downloads: 0 | Views: 18

Author(s)

Mengzhe Liang 1

Affiliation(s)

1 Moorestown Friends School, 110 E Main St, Moorestown, NJ 08057, USA

Corresponding Author

Mengzhe Liang

ABSTRACT

Race hazards, which can lead to premature asynchronous resets or erroneous state transitions, occur when concurrent signals with different propagation delays arrive at the nodes of a combinational logic circuit. This paper investigates a modulo-13 counter centered on the SN74LS161N IC. A critical race hazard scenario is constructed in Multisim by intentionally introducing signal delays, and two common suppression strategies are evaluated: (1) connecting a parallel capacitor at the reset node to form an RC low-pass filter for analog pulse smoothing; and (2) using a 74ALS175M flip-flop to edge-register the outputs before the reset logic in a structured timing approach. Simulation results demonstrate that the RC filter significantly attenuates narrow pulses at low frequencies but introduces reset latency. In contrast, the registering method transforms sub-cycle instability into clean edge-sampling, trading a one-clock-cycle delay for enhanced robustness and scalability. This study provides a practical reference for the engineering implementation of race hazard elimination in counter circuits.

KEYWORDS

Race Condition; Logic Hazard; Modulo-13 Counter; Capacitor Filtering; 74ALS175M; Multisim

CITE THIS PAPER

Mengzhe Liang, An Investigation of Race Hazard Elimination in Digital Counter Circuits. Journal of Electrotechnology, Electrical Engineering and Management (2025) Vol. 8: 141-149. DOI: http://dx.doi.org/10.23977/jeeem.2025.080117.

REFERENCES

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