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FPGA Implementation of LDPC Decoder with Low Complexity

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DOI: 10.23977/jeeem.2017.11003 | Downloads: 36 | Views: 4674


Zheng Hao 1, Li Lintao 2


1 Schoold of Information and Electronics, Beijing Institute of Technology, Beijing; 100081, China
2 School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing; 100876, China

Corresponding Author

Li Lintao


According to the limitation of resources on satellite, this paper focuses on the design and realization of low complexity LDPC decoder. A new implementation method of LDPC decoder is proposed, a various kinds of LDPC codes could be supported. Finally, a (4096, 2048) LDPC decoder is implemented for verification based on a Xilinx Vertex4 xc4vsx35 FPGA platform. The implementation result shows that only 4% FPGA logic resources were consumed and the maximum clock frequency could achieve 180MHz.


LDPC, Decoder, Low Complexity


Lintao, L. , Hao Z. (2017) FPGA Implementation of LDPC Decoder with Low Complexity. Journal of Electrotechnology, Electrical Engineering and Management (2017) 1: 12-17.


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