Clock Glitch Fault Injection Attacks on an FPGA AES Implementation
DOI: 10.23977/jeeem.2017.11005 | Downloads: 33 | Views: 2562
Zhenglin Liu 1, Yifei Qiao 1, Zhaojun Lu 1, Hailong Liu 1
1 Huazhong University of Science and Technology, Wuhan, China
Corresponding AuthorYifei Qiao
The Advanced Encryption Standard (AES) algorithm has been widely used to secure communication systems. However, the encryption algorithm is vulnerable to fault injection attacks and various attack methods have been studied. Some methods are just proposed in theory and have not been validated in practice. In this paper, we actualize a fault injection attack on an FPGA AES implementation. We propose a method to generate the highly accurate clock glitch to inject faults in the encryption process. We show that if the frequency of the clock glitch is carefully selected, only 6 faulty ciphertexts are necessary to discover the secret key.
KEYWORDSAES, Fault injection attacks, Clock glitch, FPGA
CITE THIS PAPER
Yifei Q. , Zhaojun, L. , Hailong, L. and Zhenglin L. (2017) Clock Glitch Fault Injection Attacks on an FPGA AES Implementation. Journal of Electrotechnology, Electrical Engineering and Management (2017) 1: 23-27.
 Dj.M. Maric, P.F. Meier and S.K. Estreicher: Mater. Sci. Forum Vol. 83-87 (1992), p. 119
 D. Boneh, R.A. DeMillo, and R.J. Lipton: On the importance of checking cryptographic protocols for faults, Proc. EUROCRYPT (1997), p. 37–51.
 E. Biham and A. Shamir: Differential fault analysis of secret key cryptosystems. Proc. CRYPTO (1997), p. 513–525.
 J. Bloemer and J.P. Seifert: Fault based cryptanalysis of the Advanced Encryption Standard (AES), Proc. FinancialCryptogr. (2003), p. 162–181.
 P. Dusart, G. Letourneux, and O. Vivolo: Differential fault analysis on A.E.S., Appl. Cryptogr. Netw. Security, vol. 2846 (2003), p. 293–306.
 A. Moradi, M. T. M. Shalmani, and M. Salmasizadeh: A generalized method of differential fault attack against AES cryptosystem, Proc. Int. WorkshopCryptogr. Hardware Embedded Syst. (2006), p. 91–100.
 S. Endo, T. Sugawara, N. Homma, T. Aoki, and A. Satoh: An on-chip glitchy-clock generator for testing fault injection attacks, Journal of Cryptographic Engineering (2011), p. 265–270.